1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to an output circuit of a semiconductor integrated circuit.
2. Description of the Related Art
In an output circuit of a complementary MOS (CMOS) integrated circuit, an output current is increased with the progress of semiconductor technology and expansion of its application fields.
FIG. 1 is a view showing a conventional output circuit, and FIG. 2 is a view showing an equivalent circuit of the output circuit in FIG. 1.
In FIGS. 1 and 2, an inverter circuit 11 is constituted by a p-channel MOS transistor (to be referred to as a PMOS transistor hereinafter) P1 and an n-channel MOS transistor (to be referred to as an NMOS transistor hereinafter) N1. The gates of the PMOS transistor P1 and the NMOS transistor N1 are connected to an input terminal A, the source of the PMOS transistor P1 is connected to a power supply V.sub.DD, and the source of the NMOS transistor N1 is grounded.
Both drains B of the PMOS transistor P1 and the NMOS transistor N1 are connected to a gate PG1 of a PMOS transistor P2 and to a gate NG1 of an NMOS transistor N2, respectively, and the PMOS transistor P2 and the NMOS transistor N2 constitute an output stage 12. The gates PG1 and NG1 are meandered. A plurality of sources PS2 and a plurality of drains PD2 of the PMOS transistor P2 are arranged adjacent to the gate PG1, and a plurality of sources NS2 and a plurality of drains ND2 of the NMOS transistor N2 are arranged adjacent to the gate NG1. The sources PS2 of the PMOS transistor P2 are connected to the power supply V.sub.DD, and the sources NS2 of the NMOS transistor N2 are grounded. The drains PD2 of the PMOS transistor P2 and the drains ND2 of the NMOS transistor N2 are connected to an output terminal C.
In the above conventional output circuit, the PMOS transistor P2 and the NMOS transistor N2 which constitute the output stage 12 have a larger current driving capacity than that of the PMOS transistor P1 and the NMOS transistor N1 which constitute the inverter circuit 11. Therefore, when an output signal level is switched, since a large current is supplied to the PMOS transistor P2 or the NMOS transistor N2 within a short time, large noise is generated by the output terminal C.
The same signal is supplied to the PMOS transistor P2 and the NMOS transistor N2 which constitute the output stage 12. For this reason, when the output signal level is to be switched, these transistors are simultaneously rendered conductive. Therefore, power consumption of the output circuit is increased.
Prior arts of the present invention are filed in U.S. Pat. Nos. 4,725,747 and 4,789,793.